As is known in the art, with the recent advances enable growth of both compound semiconductor (CS) devices, such as for example III-V FETS or opto-electric devices, and elemental semiconductor (ES) devices, such as for example CMOS devices on a common, such as a silicon, substrate. Thus, the term “compound semiconductor” usually refers to any non-homogeneous semiconductor layers (GaAs, InP, GaN, InSb, AlGaAs, AlGaN, . . . ) as opposed to “elemental semiconductors” (Si, Ge, . . . ). Compound semiconductors can be combination of two or more elements of the periodic table from columns III and V (GaAs, GaN, InP, AlGaAs, . . . ); II and VI (ZnO, CdSe, . . . ); IV-IV (SiGe, SiC), etc. The growth of both compound semiconductor (CS) devices and elemental semiconductor (ES) devices, is described in, for example, T. Ashley, L. Buckle, S. Datta, M. T. Emeny, D. G Hayes, K. P. Hilton, R. Jefferies, T. Martin, T. J. Philips, D. J. Wallis, P. J. Wilding and R. Chau, “Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications,” Electronics Letters, Vol. 43, No. 14, July 2007. S. Datta, G. Dewey, J. M. Fastenau, M. K. Hudait, D. Loubychev, W. K. Liu, M. Radosavljevic, W. Rachmady and R. Chau, “Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate,” IEEE Electron Device Letters, Vol. 28, No. 8, 2007, pp. 685-687. M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and Robert Chau, “Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (<2 um) Composite Buffer Architecture for High-Speed and Low-Voltage (0.5V) Logic Applications,” International Electron Devices Meeting (IEDM) Technical Digest, 2007, pp. 625-628. 
One technique used to grow both the CS devices and ES devices on the same substrate, it to provide a substrate, such a silicon substrate. A first insulating layer, such as silicon dioxide layer, is formed on the substrate. A seed layer, such as germanium, is formed on the first insulating layer, such seed layer being provided to grow, typically epitaxially, the CS devices. A second insulating layer, such as silicon dioxide is formed on the seed layer. An ES layer, such as silicon, is formed on the second insulating layer. A portion of the ES layer and underlying portions of the second insulating layer are removed to exposed portion of the seed layer. Next, a CS layer is grown on the seed layer. Next, the ES device is formed in the ES layer, and the CS device is formed on the CS layer.
Because a CS epitaxial structure needs to be grown on top of the seed layer whose crystal structure and electronic properties are different from those of the CS layer, the CS device performance may deteriorate very significantly due to the formation of an unwanted interface layer between seed and CS layers. Integration of a CS FETs onto a non-semi-insulating and non-homogeneous silicon-based substrate poses two key challenges:
1. Minimize negative substrate effects on the device performance, most notably the substrate conduction that may prevent the complete transistor pinch-off. The lack of pinch-off results in higher device's output conductance that, in turn, leads to lower AC gain, cutoff frequency, power density and drain efficiency in the transistors used in amplifier-type circuits as well as lower isolation in the transistors used in switch-type circuits.
2. Allow for low series resistance, loss series inductance and low shunt capacitance interconnect between the individual heterogeneously integrated individual CS and silicon CMOS FETs.
In accordance with the invention, a semiconductor structure is provided comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer  disposed between the first region of the compound semiconductor layer and the second region of the compound semiconductor layer. A fourth electrode is in electrical contact with the second portion of the conductive seed layer.
In one embodiment, the first, second, and fourth electrodes extend vertically downward from an upper surface of the structure.
In one embodiment, the elemental semiconductor layer is a silicon layer.
In one embodiment, the compound semiconductor layer is a III-V layer.
In one embodiment, the first semiconductor device is a MOS device.
In one embodiment, the second semiconductor device is a FET device.
In one embodiment, the third electrode is a gate electrode and wherein first and second electrodes are source and drain electrodes.
In one embodiment, the fourth electrode is in ohmic contact with the seed layer.
With such structure the first challenge is solved by providing direct control of a local electrical potential of the seed layer (e.g., germanium (Ge) layer), on top of which the CS FET epitaxial structure is deposited. This local electrical potential control is being accomplished by 1) etching away a certain shape in the CS FET and buffer vertical epitaxial structure; 2) fabricating an ohmic contact on the Ge layer and 3) isolating the Ge region under the CS FET from the rest of the Ge layer by etching a closed-shape trench in the Ge layer.
The second is solved by fabricating vertical pillars that connect the four FET electrodes (source, drain, gate, Ge layer). Following the CS FET fabrication, these pillars are formed by 1) forming a planar layer of Back-End-Of the Line (BEOL) low loss dielectric (for example BCB); 2)etching vertical holes in the BEOL dielectric; 3) filling the holes with a low resistivity metal interconnect
The effect of the electrical contact to the seed layer is to reduce the effects on CS device performance as a result of a charge layer that is inadvertently formed at the interface between the seed layer and the CS layer. This charge layer is the result of a junction (either p-n or n-n or p-p) or a quantum well that is formed when two dissimilar materials are brought into intimate contact.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 
Like reference symbols in the various drawings indicate like elements.